This invention relates to a nonvolatile semiconductor storage device and a method for using it, and more particularly to a multi-level memory, and its usage, which can store multi-level (multi-value) data in memory cells made of stacked MOS transistors.
A flash memory for storing multi-level data is disclosed in detail in ISSCC '95 Digest of Technical Papers, p. 133, for example. The memory has an architecture using flash cells as its reference cells to control the current flow into the reference cells and to cope with the read-out potential in accordance with the distribution of threshold values of the cells.
A process for reading data from a NAND flash memory includes random access for reading data of one row of memory cell arrays and for storing it in registers, and subsequent reading of the storage of the registers. When a four-value memory is to be read three times, reading and conversion into a two-value data need the time EQU 3t.sub.R +3t.sub.S +t.sub.conv
where t.sub.R is the random access time, t.sub.S is the time for reading registers, and t.sub.conv is the time for conversion into a two-value data. In a particular case where the random access time t.sub.R is 10 .mu.S, the register reading time t.sub.S is 25.6 .mu.S for reading 512 bytes in 50 nS, and the time t.sub.conv for conversion into a two-value data is 5 .mu.S, the total time for reading thrice and for conversion into two values amounts in EQU 10.times.3+25.6.times.3+5=111.8 .mu.S
The above multi-level memory involves the following problems
(1) A 2"-value memory needs n sense amplifiers. Specifically, a four-value memory needs two sense amplifiers, and an eight-value memory needs three sense amplifiers. Thus the multi-level memory requires a Larger area for sense amplifiers. PA1 (2) The number of reference cells is fixed at the time of its design and cannot be flexibly changed later. In a particular case where the number of reference cells is four, the memory must be a four-value memory even if the cells are uniform enough to realize a more-value memory. In another case where a four-value memory cannot be realized due to varieties in process parameters during fabrication, although it will be used as a two-value memory, all the sense amplifiers and other circuit elements intended for use with the four-value memory become invalid, and result in an substantial increase in cost as compared with an originally two-value memory. PA1 (3) The area occupied by sense amplifiers is too large to exactly cope with the distribution of cells within the chip. PA1 (4) Reading from a NAND flash memory takes time against the demand for high-sped reading. PA1 nonvolatile memory cells each including a source and a drain both formed on one surface of a semiconductor substrate, and including a floating gate and a control gate which are stacked on the semiconductor substrate above a portion between the source and the drain via insulation films; PA1 a word line driving circuit for applying one of a plurality of predetermined potentials to said control gates of the nonvolatile memory cells, depending on a control data introduced into said memory device; and PA1 writing and sensing circuit for applying a potential to said drains in accordance with write data introduced into said memory device and for detecting and amplifying the current flowing between the drain and the source in each said nonvolatile memory cell. PA1 when a first level of multi-level data including at least a first level and a second level is to be written, repeating a series of behaviors until writing of said first level is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said first level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not; PA1 when a second level of said multi-level data is to be written, repeating a series of behaviors until writing of said second level is completed said series of behaviors including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said second level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not. PA1 when a first level of multi-level data is to be written, repeating a series of behaviors until writing of said first level is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold level of said nonvolatile memory cell; applying a voltage responsive to said first level to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first level is finished or not; PA1 when a second level of said multi-level data is to be written, repeating a series of behaviors including a first step and a second step until writing of said second value is completed, said first step including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell by a large amount than that for writing said first value; applying a voltage responsive to said second value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first value is finished or not, and said second step including: applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell; applying a voltage responsive to said second value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first value is finished or not. PA1 when a first value of multi-level data is to be written, repeating a series of behaviors until writing of said first value is completed, said series of behaviors including: applying a predetermined write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell; applying a voltage responsive to said first value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading; and confirming whether the writing of said first value is finished or not; PA1 when a second value of said multi-level data is to be written, repeating a series of behaviors until writing of said second value is completed, said series of behaviors including: while writing said first value in said nonvolatile memory cell, applying said write voltage between said control gate and said drain to introduce a charge into said floating gate and to change the threshold value of said nonvolatile memory cell; applying a voltage responsive to said second value to said control gate and detecting and amplifying a current flowing between the source and the drain of said nonvolatile memory cell to perform verify reading: and confirming whether the writing of said first value is finished or not. PA1 a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix in which memory cells in one row are connected by a common word line and memory cells in one column are connected by a common bit line; PA1 a first register for holding a first data introduced into said memory device; PA1 a word line voltage generating circuit for generating a plurality of different voltages in response to contents held in said first register; PA1 a second register for holding a second data introduced into said memory device; PA1 a word line selecting circuit for selecting said word line in response to contents held in said second register; PA1 a word line driving circuit for driving said word line selected by said word line selecting circuit with a voltage generated by said word line voltage generating circuit; PA1 a plurality of sense amplifier circuits for detecting and amplifying the potential of said bit line and for holding data corresponding to the potential of the bit line; and PA1 a column selecting circuit for selectively outputting the data held in said sense amplifier circuits in response to a third data introduced into said memory device. PA1 a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix in which memory cells in one row are connected by a common word line and memory cells in one column are connected by a common bit line; PA1 a first register for holding a first data introduced into said memory device; PA1 a word line voltage generating circuit for generating a plurality of different voltages in response to contents held in said first register; PA1 a second register for holding a second data introduced into said memory device; PA1 a word line selecting circuit for selecting said word line in response to contents held in said second register; PA1 a word line driving circuit for driving said word line selected by said word line selecting circuit with a voltage generated by said word line voltage generating circuit; PA1 a plurality of sense amplifier circuits for detecting and amplifying the potential of said bit line and for holding data corresponding to the potential of the bit line; PA1 a column selecting circuit for selectively outputting the data held in said sense amplifier circuits in response to a third data introduced into said memory device; and PA1 a plurality of flag cells each associated with a memory cell group including a plurality of memory cells in said memory cell array to hold the number of data stored in a single memory cell in the associated memory cell group. PA1 a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix in which memory cells in one row are connected by a common word line and memory cells in one column are connected by a common bit line; PA1 a plurality of flag cells each associated with a memory cell group including a plurality of memory cells in said memory cell array to hold the number of data stored in a single memory cell in the associated memory cell group; PA1 a word line voltage generating circuit for generating a plurality of different voltages responsive to contents of said flag cells; PA1 a register for holding an address signal introduced into said memory device; PA1 a word line selecting circuit for selecting said word line in response to contents held in said second register;: PA1 a word line driving circuit for driving said word line selected by said word line selecting circuit with a voltage generated by said word line voltage generating circuit; PA1 a plurality of sense amplifier circuits for detecting and amplifying the potential of said bit line and for holding data corresponding to the potential of the bit line; and PA1 a column selecting circuit for selectively outputting the data held in said sense amplifier circuits in response to a third data introduced into said memory device. PA1 reading a flag data of a flag cell of a memory cell group to which a memory cell to be read belongs; PA1 repeating a plurality of cycles of driving a word line connected to the memory cell with a predetermined voltage pursuant to the flag data of said flag cell, then detecting and amplifying a voltage of a bit line, and outputting the read-out data; and PA1 converting the data read out in said cycles into binary data. PA1 a memory cell array including a plurality of nonvolatile memory cells arranged in a matrix in which memory cells in one row are connected by a common word line, and memory cells in one column are connected by a common bit line, and data of one row can be read out for each divisional part thereof; PA1 a serial resister aligned in parallel with said word lines in said memory cell array and capable of storing and reading individual divisional parts of data of the memory cell array independently; and PA1 a memory for storing data from said serial register for each divisional part.